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B3891 B3891 WD4003 SILICON TTINY FDZ192NZ 89LPC B3891
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  this is information on a product in full production. december 2014 docid025259 rev 2 1/22 stef4s electronic fuse for 3.3 v and 5 v lines datasheet - production data features ? power mosfet on-resistance (typ.): 40 m ? enable function ? output clamp voltage (typ.): 5.7 v in 5 v mode, and 3.8 v in 3.3 v mode ? undervoltage lockout ? short-circuit limit ? overload foldback current limit ? controlled soft-start ? thermal auto-retry ? internal sensing fet ? operative temp. range: - 40 c to 85 c ? available in dfn 3x3 10l package description the stef4s is an integrated electronic fuse optimized for monitoring the output current and the input voltage. it can be connected in series to 3.3 v or 5 v rails, protecting the electronic circuitry on its output from overcurrent and overvoltage. the operating mode (5 v or 3.3 v) can be selected by a dedicated pin. the stef4s has a controlled turn-on time, adjustable by an external capacitor. when an overload condition occurs the device limits the output current to a predefined safe value. if the anomalous overload condition persists it goes into an open state, disconnecting the load from the power supply. if a continuous short-circuit is present on the board, the e-fuse limits the output current to a safe value. in case of overvoltage on the input, the device clamps the output voltage to a predefined value and protects the load. if the anomalous fault condition persists, the internal thermal protection circuit shuts down the device and then automatically attempts to re- supply the load until the fault condition is removed. unlike mechanical fuses, which must be physically replaced after a single event, the e- fuse does not degrade in its performance after short-circuit/thermal protection interventions. applications ? hard disk drives ? solid state drives (ssd) ? hard disk and ssd arrays ? set-top boxes ? dvd and blu-ray disc drivers ')1[/ table 1. device summary order code package packing STEF4SPUR dfn 3x3 - 10l tape and reel www.st.com
contents stef4s 2/22 docid025259 rev 2 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.1.1 turn-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.1.2 normal operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.1.3 output voltage clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.1.4 current limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.1.5 thermal shutdown and auto-retry function . . . . . . . . . . . . . . . . . . . . . . . 9 5.2 startup time and css calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.3 uvlo and voltage clamp selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.4 enable pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.1 dfn6 3x3 - 10l package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.2 dfn6 3x3 - 10l packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
docid025259 rev 2 3/22 stef4s block diagram 22 1 block diagram figure 1. device block diagram $09
pin configuration stef4s 4/22 docid025259 rev 2 2 pin configuration figure 2. pin configuration (top view) $09 9 ,1 9 ,1 9 ,1 9 &3 *1' 9 287 9 287 9 287 (1 667   *1'         table 2. pin description pin n symbol note 1, 2, 3 v in input supply voltage pin 4v cp voltage clamping and uvlo selection pin (high state 5 v, low state 3.3 v) 5 gnd ground pin (can be left floating if tab is connected to gnd) 6 sst soft-start time selection pin. a capacitor can be connected between this pin and gnd to increase the startup time 7 en enable pin (active high) 8,9,10 v out output voltage pin exp gnd exposed pad is internally connected to gnd
docid025259 rev 2 5/22 stef4s maximum ratings 22 3 maximum ratings note: absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. table 3. absolute maximum ratings symbol parameter value unit v in positive power supply voltage -0.3 to 15 v v out output voltage -0.3 to 7 v v cp uvlo and voltage clamp selection pin -0.3 to v in v en enable pin -0.3 to v in v sst soft-start time selection pin -0.3 to 4.6 v t j max. junction temperature (1) -40 to 125 c t stg storage temperature range -65 to 150 c t lead lead temperature (soldering) 10 s 260 c 1. the thermal limit is set above the maximum thermal rating. it is not recommended the device to operate at temperatures greater than the maximum ratings for extended periods of time. table 4. thermal data symbol parameter value unit r thja thermal resistance junction-ambient 40 c/w r thjc thermal resistance junction-case 2.5 c/w
electrical characteristics stef4s 6/22 docid025259 rev 2 4 electrical characteristics unless otherwise specified, typical values are referred to v in = 5 v for v cp = v in and v in = 3.3 v for v cp = gnd,c in = c out = 22 f, t = 25 oc, min. and max. values are referred to t = - 40 oc to 85 oc. table 5. stef4s electrical characteristic symbol parameter test conditions min. typ. max. unit v in operating input voltage 10 v under/overvoltage protection, 3.3 v mode v clamp output clamping voltage v in = 10 v, v cp = gnd 3.6 3.8 4.0 v v uvlo under voltage lockout v cp = gnd, turn-on, voltage going up 2.2 2.3 2.4 v v hyst uvlo hysteresis v cp = gnd 50 90 130 mv under/overvoltage protection, 5 v mode v clamp output clamping voltage v in = 10 v, v cp = v in 5.4 5.7 6.0 v v uvlo under voltage lockout v cp = v in , turn-on, voltage going up 3.4 3.6 3.8 v v hyst uvlo hysteresis v cp = v in 60 105 150 mv power mosfet r ds(on) on-resistance r ds(on) = (v in -v out )/i out 40 m t j = 85 c (1) 70 current limit i ol protection trip current 5 a i lim overload current limit 5 7 9 a i short short-circuit current limit v out = 0 v 3 a soft-start circuit t ss output voltage ramp time from v in = v uvlo to v out = 90 %, no c ss 0.6 ms from v in = v uvlo to v out = 90 %, c ss = 100 nf 16 23 30 enable pin thresholds v en-l enable pin switch-off voltage output disabled 0.4 v v en-h enable pin switch-on voltage output enabled 2 v v cp pin thresholds v cp-l 3.3 v mode selection threshold 3.3 v mode enabled 0.4 v v cp-h 5 v mode selection threshold 5 v mode enabled 2 v total device
docid025259 rev 2 7/22 stef4s electrical characteristics 22 i bias bias current on state, v en = v in = 5 v 50 65 a off state, v en = gnd, v in = 5 v 15 v min minimum operating voltage device is in off state (v out = 0) 2 v thermal latch tsd shutdown temperature 140 c hysteresis 20 1. guaranteed by design, not tested in production. table 5. stef4s electrical characteristic (continued) symbol parameter test conditions min. typ. max. unit
typical characteristics stef4s 8/22 docid025259 rev 2 5 typical characteristics figure 3. application circuit $09 ? ) ? ) $ 065
docid025259 rev 2 9/22 stef4s typical characteristics 22 5.1 operating modes 5.1.1 turn-on when the input voltage is applied and the en pin is high, the output voltage is supplied with a slope defined by the internal dv/dt circuitry. if no additional capacitor is connected to c ss pin, the total time from the enable signal going high and the output voltage reaching the nominal value is around 0.6 ms. 5.1.2 normal operating condition the stef4s e-fuse behaves like a mechanical fuse, buffering the circuitry on its output with the same voltage shown at its input, apart from a small voltage fall due to the mosfet r ds(on) . 5.1.3 output voltage clamp the internal voltage clamp circuit clamps the output voltage to the v clamp values reported in ta ble 5 if the input voltage exceeds the typical thresholds of 3.8 v in the 3.3 v mode and 5.7 v in the 5 v mode. 5.1.4 current limiting when an overload event occurs, the current limiting circuit reduces the conductivity of the power mosfet, in order to clamp the input current at the pre-programmed value. the current limit circuit has a foldback characteristic to reduce the power dissipation over the power mosfet in short-circuit condition. 5.1.5 thermal shutdown and auto-retry function if the device temperature exceeds the thermal shutdown threshold, typically 140 c, the thermal shutdown circuitry turns the power mosfet off and disconnects the load. once the die temperature has decreased about 20 c the device automatically attempts to apply again the power to the load (auto-retry). this cycle persists until the fault condition is removed. 5.2 startup time and c ss calculation connecting a capacitor between the c ss pin and gnd allows the modification of the output voltage startup time.the startup time (t ss ) is defined as the time interval between the device uvlo threshold, which has been overcome, and v out , which has reached 90% of the nominal value as shown in figure 4 . the below table 6 shows the typical startup time obtained with the industry-standard values of c ss . table 6. startup time vs. c ss capacitor value parameter value c ss [nf] none 10 47 100 t ss [ms] 0.6 2.3 10.8 23
typical characteristics stef4s 10/22 docid025259 rev 2 the capacitance to be added to c ss pin can be also estimated by using the following theoretical formula: equation 1 the above value is not valid if c ss is not connected. c ss is expressed in farad and the time in seconds. a ceramic low leakage capacitor is suggested for this purpose. the formula is meant as a theoretical support to choose the c ss capacitor and it does not take into account the capacitor tolerance, temperature and process variations. figure 4. startup time 5.3 uvlo and voltage clamp selection the device can be used either on the 3.3 v or on the 5 v lines. the operating mode can be selected through the v cp pin. if this pin is set at high level (v cp > 2 v) the operating mode is 5 v. in this mode the uvlo threshold is 3.6 v typical, the clamping voltage is set to 5.7 v. if the v cp pin is pulled to low level (v cp < 0.4 v), the operating mode is 3.3 v. in this mode the uvlo threshold is 2.3 v typical, the clamping voltage is set to 3.8 v. 5.4 enable pin the en pin is used to turn on/off the device. the device is disabled when the en pin voltage is lower than 0.4 v, enabled if the en pin voltage is higher than 2 v. c ss 4.35 10 6 ? tss = $09 $0
docid025259 rev 2 11/22 stef4s typical performance characteristics 22 6 typical performance characteristics (the following plots are referred to the typical application circuit and, unless otherwise noted, at t a = 25 c) figure 5. r ds(on) vs temperature (3.3 v) figure 6. r ds(on) vs temperature (5 v) figure 7. clamping voltage vs temperature (3.3 v) figure 8. clamping voltage vs temperature (5 v) $09                      5'621>p @ 7hpshudwxuh> ?&@ ,rxw$ ,rxw$ 9 && 99 &3 *1' $09 9 && 99 &3 *1'            rer? ?e??e 5'621>p @ ,rxw$ ,rxw$ 7hpshudwxuh> ?&@ $09 9 ,1 99 &3 *1'                   9 &/$03 >9@ 7hpshudwxuh> ?&@ $09 9 ,1 9 &3 9                   9 &/$03 >9@ 7hpshudwxuh> ?&@
typical performance characteristics stef4s 12/22 docid025259 rev 2 figure 9. uvlo threshold vs temperature (3.3 v) figure 10. uvlo threshold vs temperature (5 v) $09 9 &3 *1'7xuq2qyrowdjhjrlqjxs                     9 89/2 >9@ 7hpshudwxuh> ? &@ $09                 9 89/2 >9@ 7hpshudwxuh> ?&@ 9 &3 9 ,1 7xuq 2qyrowdjhjrlqjxs figure 11. bias current vs temperature (3.3 v) figure 12. bias current vs temperature (5 v) $09                 , %,$6 >?$@ 7hpshudwxuh> ?&@ 9 (1 9 ,1 9 &3 *1' $09                , %,$6 >?$@ 7hpshudwxuh> ?&@ 9 (1 9 ,1 9 &3 9 figure 13. shutdown current vs temperature (3.3 v) figure 14. shutdown current vs temperature (5 v) $09 9 ,1 9 (1 9 &3 *1'               , %,$6 >?$@ 7hpshudwxuh> ?&@ $09 9 ,1 9 &3 9 9 (1 *1'               , %,$6 >?$@ 7hpshudwxuh> ?&@
docid025259 rev 2 13/22 stef4s typical performance characteristics 22 figure 15. trip point, overload and short-circuit current (3.3 v) figure 16. trip point, overload and short-circuit current (5 v) figure 17. startup into short-circuit (3.3 v) figure 18. startup into short-circuit (5 v) figure 19. soft-start behavior (3.3 v) figure 20. soft-start behavior (5 v) $09 $09 $09 $09 $09 9 ,1 9& ,1 & 287 ?)9 &3 *1'& 667  q) $09 9 ,1 9& ,1 & 287 ?)9 &3 *1'& 667  q) 9 ,1  9 9 9 9       & & & ,1 ,1 ,1 ,1 & & & & 287 2 28 2 28 2 28 2 287 2 2 2 2 2 2 2 2 28 2 2 2 87 2 2 2 2 2 28 28 2 2 2 87 2 2   ?) ? ? ? 9   &3 & & & & & & & & & & & & & & & & & & & & & & & &3 & & & & & &3 & & &3 & & & * 1 ' ' ' '   & 667 7 7 7 7 7 667 7 7 7 667 7 667 7    q) ) ) ) q q) q) ) ) ) q q q q q q q q q) q) ) ) ) ) ) ) ) q q q q q q q q q q ) ) ) ) ) ) ) ) ) )  
package information stef4s 14/22 docid025259 rev 2 7 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
docid025259 rev 2 15/22 stef4s package information 22 7.1 dfn6 3x3 - 10l package information figure 21. dfn6 3x3 - 10l package outline b%
package information stef4s 16/22 docid025259 rev 2 table 7. dfn6 3x3 - 10l mechanical data dim. mm min. typ. max. a 0.70 0.75 0.80 a1 0.00 0.02 0.05 b 0.18 0.25 0.30 d3.00 e3.00 e0.5 d2 2.234 2.384 2.484 e2 1.496 1.646 1.746 k0.20 l 0.30 0.40 0.50 aaa 0.05 bbb 0.10 ccc 0.10 ddd 0.05 eee 0.08
docid025259 rev 2 17/22 stef4s package information 22 figure 22. dfn6 3x3 - 10l recommended footprint b%
package information stef4s 18/22 docid025259 rev 2 7.2 dfn6 3x3 - 10l packing information figure 23. tape for dfn6 3x3 - 10l b1
docid025259 rev 2 19/22 stef4s package information 22 figure 24. reel for dfn6 3x3 - 10l figure 25. schematic drawing orientation b1
package information stef4s 20/22 docid025259 rev 2 table 8. dfn6 3x3 10l tape and reel mechanical data dim. mm min. typ. max. a0 3.20 3.30 3.40 b0 3.20 3.30 3.40 k0 1 1.10 1.20
docid025259 rev 2 21/22 stef4s revision history 22 8 revision history table 9. document revision history date revision changes 23-oct-2013 1 initial release. 02-dec-2014 2 updated section 4: electrical characteristics , section 7: package information and figure 3: application circuit . minor text changes.
stef4s 22/22 docid025259 rev 2 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics ? all rights reserved


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